HiPC 2016 Keynotes
Slides of the keynote presentations are now available
Genomes Galore: Big Data Challenges in the Life Sciences, Srinivas Aluru
China’s HPC development in the next 5 years, Depei Qian
Toward Extreme-Scale Processor Chips, Josep Torrellas
After a brief review of HPC research and development in China’s high-tech R&D program, this talk will introduce the plan of HPC development under the new Key R&D Program of China in the thirteenth 5-year plan. The major challenges in establishing the eco-system for high performance computing in China will be discussed, including the technical issues in developing the next generation high performance computers, the need for developing system/application software for the systems based on domestically developed processors, and the mechanism for establishing a sustainable national HPC environment. The goal and the major activities of the new key project on HPC will be presented.
Depei Qian is currently a professor at Sun Yat-sen University and Beihang University and serves as Dean of the School of Data and Computer Science at Sun Yat-sen University. He has been working on computer architecture and computer networks for many years. His current research interests include high performance computer architecture and implementation technologies, distributed computing, network management and network performance measurement. He has published over 300 papers in journals and conferences. Since 1996, he has been a member of the expert group and expert committee of the National High-tech Research and Development Program (the 863 program) in information technology. He has been chief scientist of three 863 key projects on high performance computing since 2002. Currently, he is the chief scientist of the 863 key project on high productivity computer and application service environment.
As transistor sizes continue to scale, we are about to witness stunning levels of chip integration, with 1,000 cores on a single die, and increasing levels of die stacking. Transistors may not be much faster, but there will be many more of them. In these architectures, efficient communication and synchronization will be a challenge. Moreover, energy and power will constrain the designs even more than they do today. In this context, this talk presents some of the technologies that we may need to deploy to exploit these architectures. To enable data sharing, we need novel synchronization and fence hardware. For low-latency communication, we may leverage on-chip wireless networks. Cores need to be voltage scalable, i.e., flexibly operate both at high and low voltage ranges. Techniques for efficient energy use need to be widespread. Finally, hardware extensions to ease programming will provide a competitive edge. A combination of all of these techniques --and more-- are needed.
Josep Torrellas is the Saburo Muroga Professor of Computer Science at the University of Illinois at Urbana-Champaign. He is a Fellow of IEEE and ACM. He is the Director of the Center for Programmable Extreme-Scale Computing, a center focused on architectures for extreme energy and power efficiency. He was until recently the Director of the Intel-Illinois Parallelism Center (I2PC), a center created by Intel to advance parallel computing. He has made contributions to parallel computer architecture in the areas of shared memory multiprocessor organizations, cache hierarchies and coherence protocols, thread-level speculation, and hardware and software reliability. He received the 2015 IEEE CS Technical Achievement Award.